Alibaba XuanTie C950 5nm RISC-V chip runs Qwen3.8-27B natively

On August 19, 2026, Alibaba T-Head announced that its 5nm RISC-V server CPU XuanTie C950 (64 cores) achieved Day 0 adaptation of the Qwen3.8-27B large model. The model decodes at approximately 30 tokens/s in a native environment with 1.9s first-token latency, requiring no GPU or emulation layer.This is the first time a 27-billion-parameter AI model has run directly on a RISC-V architecture. Key technical highlights include chip-level tensor compute unit optimization, efficient memory bandwidth utilization, and hardware-level acceleration for Transformer architectures.The result challenges the conventional view that LLM inference must depend on GPUs, demonstrating RISC-V's potential in AI inference scenarios. For edge computing and end-side AI deployment, this means large models can run on lower-power, lower-cost chips.Counterpoint Research previously noted that on-device compute is becoming the next focus of the AI industry, with local deployment offering fast response and strong security. Alibaba had also completed Day-0 adaptation of Qwen3.8-27B on MediaTek Dimensity C-X1 automotive cockpit and Dimensity flagship mobile chips on Aug 14.